1. Field of Invention
The present invention relates to an integrated circuit (IC) process. More particularly, the present invention relates to a method for fabricating a node contact opening.
2. Description of Related Art
Conventionally, in the IC process for dynamic random access memory (DRAM), an oxide layer is deposited after the formation of the metal oxide semiconductor (MOS). A bit line, which couples electrically with the substrate, is formed on the oxide layer before performing the capacitor process. A further oxide layer is deposited on the bit line and partially removed by photolithography and etching to form a node contact opening. As the node contact opening is etched for a longer duration due to its higher aspect ratio, a thicker pattern photoresist is required to adequately reduce the pattern distortion, which occurs during the long etching process. However, the thicker pattern photoresist has inevitably caused the problem of poorer focus window.
As the device size becomes smaller, the bit line is also easily exposed during the etching for the node contact opening, so that a short-circuiting occurs between the subsequently formed capacitor and the bit line. Although a silicon nitride spacer is formed on the sidewall of the opening, the substrate may still be exposed in the etching environment during the etching step for forming the silicon nitride spacer. This increases the possibility of the single cell substrate being damaged, thus influencing the reliability of the device.